ONLINE ISSN : 1745-1337 PRINT ISSN : 0916-8508

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91.A (2008) , No. 4 pp.1044-1053

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Novel Register Sharing in Datapath for Structural Robustness against Delay Variation Keisuke INOUE1)2), Mineo KANEKO1)2) and Tsuyoshi IWAGAKI1)2) 1) School of Information Science, Japan Advanced Institute of Science and Technology 2) The Institute of Electronics, Information and Communication Engineers (Manuscript received: June 26, 2007) SUMMARY  As the feature size of VLSI becomes smaller, delay variations become a serious problem in VLSI. In this paper, we propose a novel class of robustness for a datapath against delay variations, which is named structural robustness against delay variation (SRV), and propose sufficient conditions for a datapath to have SRV. A resultant circuit designed under these conditions has a larger timing margin to delay variations than previous designs without sacrificing effective computation time. In addition, under any degree of delay variations, we can always find an available clock frequency for a datapath having SRV property to operate correctly, which could be a preferable characteristic in IP-based design. Key words:  datapath synthesis, delay variation, register assignment, setup and hold constraints

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	To cite this article:
	Keisuke INOUE, Mineo KANEKO and Tsuyoshi IWAGAKI, “Novel Register Sharing in Datapath for Structural Robustness against Delay Variation”, IEICE Trans. Fundamentals, Vol. E91.A, No. 4, pp.1044-1053, 2008 .

	doi:10.1093/ietfec/e91-a.4.1044
	JOI  JST.JSTAGE/transfun/E91.A.1044

Copyright (c) 2010 The Institute of Electronics, Information and Communication Engineers

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