A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM

Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi; Koji Tsunoda; Toshihiro Sugii

doi:10.2197/ipsjtsldm.9.79

Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii

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Keywords: non-volatile memory, STT-MRAM, Low-Voltage, process variation tolerance

JOURNAL FREE ACCESS

2016 Volume 9 Pages 79-83

DOI https://doi.org/10.2197/ipsjtsldm.9.79

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Abstract

In this paper, in order to realize 0.4V operation of STT-MRAM, we propose the counter base read circuit. The proposed read circuit has tolerance for process variation and temperature fluctuation by changing dynamically the load curve in a time-axis at the read operation. We confirmed that the proposed read circuit can operate at the conditions of five process corners (TT, FF, FS, SF, and SS) and three temperatures (-20°C, 25°C, and 100°C) by HSPICE simulations. At the condition of TT corner and 25°C, read time of the proposed circuit is 271ns, and energy consumption is 1.05pJ at “1” read operation and 1.23pJ at “0” read operation.

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