This work presents a novel counter-based randomization method for use in a flying-adder frequency synthesizer with a cost-effective structure that can replace the fractional accumulator. The proposed technique involves a counter, a comparator and a modified linear feedback shift register. The power consumption and speed bottleneck of the conventional flying-adder are significantly reduced. The modified linear shift feedback register is used as a pseudo random data generator, suppressing the spurious tones arise from the periodic carry sequences that is generated by the fractional accumulator. Furthermore, the proposed counter-based randomization method greatly reduces the large memory size that is required by the conventional approach to carry randomization. A test chip for the proposed counter-based randomization method is fabricated in the TSMC 0.18 μm 1P6M CMOS process, with the core area of 0.093 mm². The output frequency had a range of 43.4 MHz ∼ 225.8 MHz at 1.8 V with peak-to-peak jitter (Pk-Pk) jitter 139.2 ps at 225.8 MHz. Power consumption is 2.8 mW @ 225.8 MHz with 1.8 supply voltage.