Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation

Shumpei MORITA; Song BIAN; Michihiro SHINTANI; Masayuki HIROMOTO; Takashi SATO

doi:10.1587/transfun.E100.A.1464

Special Section on Design Methodologies for System on a Chip

Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation

Shumpei MORITA, Song BIAN, Michihiro SHINTANI, Masayuki HIROMOTO, Takashi SATO

Author information

Keywords: NBTI mitigation, reliability, transistor aging, performance degradation, internal node control

JOURNAL RESTRICTED ACCESS

2017 Volume E100.A Issue 7 Pages 1464-1472

DOI https://doi.org/10.1587/transfun.E100.A.1464

Details

Abstract

Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation due to NBTI. We propose a path clustering approach to accelerate finding effective replacement gates. Upon the observation that there exist paths that always become timing critical after aging, critical path candidates are clustered to select representative path in each cluster. With efficient data structure to further reduce timing calculation, INC logic optimization has first became tractable in practical time. Through the experiments using a processor, 171x speedup has been demonstrated while retaining almost the same level of mitigation gain.

Corresponding author

Register with J-STAGE for free!