Host: Japan Institute of Electronics Packaging
In this paper, we propose a fast transient simulation technique using LIMwith the multi-rate latency technique. In this work, the time step size isselected according to the LC value of each part of the network. This methodcan reduce the calculation cost without violating the stability criterion.Furthermore, we describe a method for including the CMOS invertercharacteristics into LIM. Since its implementation is explicitrepresentation, it can perform the analysis without the iterative methodsuch as Newton-Raphson algorithm that is generally used for nonlinearelements. Finally, some circuit simulations with the example networks areperformed with the proposed method. From the simulation results, thevalidity and the efficiency of this technique is verified
