Upscaling the Electrochemical Porosification of Silicon — A Theoretical and Experimental Process Analysis

抄録

The transition from laboratory-scale experiments to industrial-scale production frequently exposes fundamental challenges related to process similarity. In the context of silicon porosification, achieving consistent results during scale-up requires maintaining thermal, kinematic, geometric, and electrochemical (current/potential) similarities. On the example of two stages of upscaling, this work aims to elucidate the principal scaling effects that arise during the electrochemical porosification of silicon and to outline strategies for mitigating them. Through a series of representative examples, the paper highlights how process parameters, reactor geometry, and operating modes influence the resulting pore architecture and uniformity. A novel inline etching tool is presented where the wafers pass over tanks of alternating polarity. This approach has the great benefit that it does not need a backside contact; however, the alternating tank coverage leads to current density fluctuations under potentiostatic operation. A simple COMSOL simulation (Finite Element Method) of the series resistance network of the system is able to explain the fluctuations qualitatively as well as quantitatively. On this basis, design rules for the next-generation inline etching tool are suggested that would reduce the current density fluctuations from about 50 % to less than 10 %.