IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
A high-throughput fixed-point complex divider for FPGAs
Dong WangPengju RenLeibo Liu
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JOURNALS FREE ACCESS

2013 Volume 10 Issue 4 Pages 20120879

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Abstract

This paper presents a high-throughput fixed-point complex divider which uses four pipelined CORDIC units to transform and divide complex numbers in Polar coordinates. By persevering the macro-angle for CORDIC rotations in redundant form and developing an optimized pipelining structure, the FPGA based implementation achieves a 9× advantage on throughput over the best design reported. In addition, the final error is guaranteed within 1ulp (unit in last position). Thus the proposed complex divider is highly suitable for accelerating DSP applications with high precision numerical accuracy requirements.

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© 2013 by The Institute of Electronics, Information and Communication Engineers
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