IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Versatile stream buffer architecture to exploit the high memory bandwidth of 3-D IC technology
Hong-Yeol LimGi-Ho Park
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2013 Volume 10 Issue 4 Pages 20120971

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Abstract

Three-dimensional (3-D) integration technology provides various architectural opportunities including huge memory bandwidth. This paper proposes versatile stream buffer architecture to work as a secondary victim cache as well as the conventional stream buffer. The versatile stream buffer utilizes empty spaces to exploit massive memory bandwidth provided by 3-D integration technology and to reduce memory access frequency. Performance evaluation results show that the proposed mechanism with a 16KB stream buffer and a 4KB victim cache can achieve better performance than the conventional L2 cache with the capacity of 256KB and 2MB by 10% and 3%, respectively. The proposed mechanism reduces the miss rate by about 12% more than the conventional L2 cache with the capacity of 256KB.

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© 2013 by The Institute of Electronics, Information and Communication Engineers
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