2013 Volume 10 Issue 7 Pages 20130161
A high-performance VLSI architecture for H.265/HEVC loop filter is proposed. The architecture is implemented by a parallel register array that consists of 8×8 registers with two data flow directions. The register array computes the sub-blocks of four different coding tree blocks at the same time based on the analysis of the computation order. This leads to the small number of registers used in the register array. The architecture computes 4K UHD at 30fps in real-time. The size of the synthesized design is 54K gates. The operating clock frequency is 225MHz in TSMC 65nm process. If the degree of parallelism is increased to four, the architecture can compute up to 8K UHD at 60fps.