IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A low jitter clock and data recovery with a single edge sensing Bang-Bang PD
Taek-Joon AhnSang-Soon ImYong-Sung AhnJin-Ku Kang
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2014 Volume 11 Issue 7 Pages 20140088

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Abstract

This letter describes a low jitter clock and data recovery (CDR) circuit with a modified bang-bang phase detector (BBPD). The proposed PD senses the phase relationship using a single edge of input data to reduce ripples in the VCO control voltage. A 2.5Gbps CDR circuit with a proposed BBPD has been designed and compared with conventional BBPD using 0.13μm CMOS technology. Measured results reveal that proposed CDR shows the peak-to-peak jitter of 17ps on 25−1 PRBS input pattern compared to 26ps with the CDR with a conventional BBPD. The proposed CDR can be best applied to 8B10B encoded input data. Power consumption can also be saved by about 3mW with the proposed BBPD.

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© 2014 by The Institute of Electronics, Information and Communication Engineers
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