2015 Volume 12 Issue 12 Pages 20150284
A wide-range and fast-locking all digital successive approximation register-controlled delay-locked loop (SARDLL) is presented for dynamic voltage/frequency scaling (DVFS) system-on-chips (SoCs). The proposed SARDLL eliminates the harmonic lock problem and zero-delay trap problem by using the improved resettable digitally controlled delay line (DCDL) and shortens the lock time by adopting the 2-b successive-approximation-register (SAR) algorithm. The proposed 6-bit SARDLL is designed using the TSMC 65 nm CMOS low power cell library. The layout’s active area is 91 µm × 91 µm. The post-layout simulation results show that the proposed SARDLL can operate from 250 MHz to 2 GHz. Its lock time is constant 9 cycles of the input clock. The power consumption is estimated to be 0.72 mW at 1.2 V supply voltage and 2-GHz clock frequency.