IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Parallelizing SHA-1
Hu-ung LeeSeongjing LeeJae-woon KimYoujip Won
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JOURNALS FREE ACCESS

2015 Volume 12 Issue 12 Pages 20150371

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Abstract

In this paper, we propose the parallel architecture for high speed calculations of SHA-1, a widely used cryptographic hash function. Parallel SHA-1 consists of a number of base modules which process the message digest in parallel manner. The base module uses state of art SHA-1 acceleration techniques: loop unfolding, pre-processing, and pipelining. We achieved the performance improvement of 5.8% over the pipeline architecture that is known to have nearly achieved the theoretical performance limit. We implemented our system on the Xilinx Virtex-6 FPGA and verified the operations by interfacing it with MicroBlaze soft processor core.

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© 2015 by The Institute of Electronics, Information and Communication Engineers
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