IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Reduced-code test method using sub-histograms for pipelined ADCs
Hyeonuk SonJaewon JangHeetae KimSungho Kang
Author information
JOURNALS FREE ACCESS

2015 Volume 12 Issue 12 Pages 20150417

Details
Abstract

The measurement of static test parameters for an analog-to-digital converter (ADC) requires a large volume of test data, especially for a high-resolution ADC. This paper proposes a reduced-code test method for pipelined ADCs that does not compromise test accuracy. The proposed method calculates fault information at each stage by using sub-histograms. The simulation results based on 12-bit pipelined ADCs show a maximum integral nonlinearity error of 0.590 LSB with only 3.92% of the codes required for the conventional histogram-based method.

Information related to the author
© 2015 by The Institute of Electronics, Information and Communication Engineers
Previous article Next article
feedback
Top