IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
New systolic modular multiplication architecture for efficient Montgomery multiplication
Se-Hyu ChoiKeon-Jik Lee
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2015 Volume 12 Issue 2 Pages 20141051

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Abstract

We propose a new low complexity Montgomery algorithm enabling the efficient selection of the quotient value necessary for an exact division in Montgomery multiplication. We also present two new systolic multipliers which use similar data flows as described in the most significant bit (MSB)-first GF(2m) multiplier in [1]. The proposed parallel and serial multipliers have less hardware and time complexities compared to related multiplier. The serial multiplier can be well applied to space-limited hardware. Furthermore, our proposed systolic multipliers include regularity, modularity, local interconnection, and unidirectional data flow features.

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© 2015 by The Institute of Electronics, Information and Communication Engineers
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