A 270-MS/s 6-b SAR ADC with preamplifier sharing and self-locking comparators

Abstract

This paper presents a high speed SAR ADC with distributed comparators and shared preamplifiers. In contrast with the previous design, the sharing preamplifier technique avoids input range degradation and comparators’ offset calibration. Also, the paper proposes a self-locking dynamic comparator to maintain its high speed and high robustness. Moreover, it consumes less power than traditional single cross-coupling comparator. The ADC is fabricated in 0.13 µm CMOS technology to achieve a performance of 6-b resolution at 270-MSps rate. Its power consumption is 4.25 mW under a supply of 1.2 V. The measurement results shows the ADC achieves an ENOB of 5.65b with a low frequency input and 5.17b with a up-to-Nyquist frequency input. The FoM of the proposed ADC is 313-fJ/conversion step.