IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
An ultra-long FFT architecture implemented in a reconfigurable application specified processor
Feng HanLi LiKun WangFan FengHongbing PanBaoning ZhangGuoqiang HeJun Lin
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JOURNAL FREE ACCESS

2016 Volume 13 Issue 13 Pages 20160504

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Abstract

This paper presents an efficient architecture for performing 128 points to 1M points Fast Fourier Transformation (FFT) based on mixed radix-2/4/8 butterfly unit. The proposed FFT architecture reduces the computation cost by taking the advantage of the radix-8 FFT algorithm while remaining compatible with sequences whose data length is an integral power of 2. Further optimizations for reconfigurable application specified processor are developed. First, we propose a separated radix-2/4/8 butterfly unit which is more flexible than an entire radix-2/4/8 butterfly unit; second, for the sequences longer than 256K points, an efficient 2-epoch FFT solution is realized. This FFT architecture is implemented in a reconfigurable application specified processor. The computation time of our architecture is 676 us and 14.8 ms for 128K and 1M points FFTs respectively.

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© 2016 by The Institute of Electronics, Information and Communication Engineers
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