IEICE Electronics Express
Online ISSN : 1349-2543
A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler
Xincun JiXiaojuan XiaZixuan WangLeisheng Jin
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2017 Volume 14 Issue 8 Pages 20170065


A 2.4 GHz fractional-N PLL implemented in 65-nm CMOS process is presented in this letter. A TSPC dual-modulus prescaler is proposed to reduce the PLL’s power consumption by merging one of the branches of the true single-phase clocked (TSPC) D flip-flops. The measured synthesizer output frequency ranges from 2.16 to 2.7 GHz, and consumes 8 mW from a 1.3 V power supply. The in-band phase noise is −98 dBc/Hz at 100 kHz offset, and −115 dBc/Hz at 1 MHz offset at a carrier frequency of 2.438 GHz. The circuit achieves the RMS jitter of 0.86 ps and figure of merit of −230 dB, with the fractional spurs below −55 dBc.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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