IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
VLSI design of a power-efficient object detector using PCANet
Yuteng ZhouXinming Huang
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JOURNALS FREE ACCESS

2018 Volume 15 Issue 12 Pages 20180396

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Abstract

This paper presents the hardware architecture and VLSI implementations of a PCANet-based object detector. The proposed PCANet model, cascaded with a linear support vector machine, can achieve better classification performance than traditional handcrafted computer vision methods, yet it is significantly more power efficient than multi-layer convolutional neural networks. The proposed pipeline hardware architecture, when implemented using Synopsys 32 nm process technology, results in 27.4 fps while processing 1080P, with only 0.5 watt power consumption. Targeted for the application of advanced driver assistance system, the proposed design is evaluated on road marking and traffic light dataset with an accuracy result of 96.8% and 93.1% respectively. Therefore, the proposed VLSI implementation of PCANet algorithm provides a high-throughput and power-efficient solution for object detection applications.

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© 2018 by The Institute of Electronics, Information and Communication Engineers
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