A new area and power efficient DCT circuits using sporadic logarithmic shifters

Abstract

Discrete Cosine Transform (DCT) is by far the most widely adopted transformation in digital image and video processing. Particularly for applications in mobile and smart devices, the required DCT needs to be realized with small circuit area and low power cost. In this paper, a new area- and power-efficient DCT architecture design is proposed. To reduce the area and power cost, temporal redundancy in matrix-vector multiplication is eliminated by time-multiplexing reconfigurable multipliers. To further reduce the complexity, a new minimization algorithm is proposed to maximize the utilization of the newly developed sporadic programmable shifters. Our experimental results on FPGA show significant circuit area reduction by at least 39.0% and power-efficiency improvement by at least 12.3% over existing advanced DCT circuits reported in the literature.