A 0.07–3 GHz wideband front-end for SDR receiver with 2.3 dB NF and 12 dBm IIP₃ in 65 nm CMOS

Abstract

This paper presents a wideband (0.07–3 GHz) receiver front-end realized in 65 nm CMOS technology for mobile Software-Defined Radio (SDR) applications. A more power-efficient wideband common-gate low-noise amplifier (LNA) featuring a common-source path for noise-canceling is proposed to trade-off linearity and noise figure (NF). A current commutating down conversion passive mixer with transimpedance amplifier is applied to achieve low flicker noise and high linearity with low supply voltage. Measurements show that the front-end achieves conversion gain higher than 42 dB. The measured NF ranges from 2.28 to 3.68 dB in the covered frequency range and IIP₃ varies from 9 to 12 dBm versus different frequencies. The front-end occupies an active area of 0.8 mm² and consumes a power of 40 mW from 1.2 V supply voltage.