2020 Volume 17 Issue 10 Pages 20200090
The development of DRAM cannot meet the low power requirement of IoT applications due to the high refresh power. As one of new non-volatile memory, STT-MRAM has extremely low static power, high read performance and high endurance. In this paper, we build a hybrid DRAM and STT-MRAM main memory to reduce energy. Considering STT-MRAM’s high write power and high write latency, we propose a fast cacheline-based data replacement to reduce write operations of STT-MRAM. The results show that the hybrid DRAM and STT-MRAM main memory can provide comparable performance to DRAM, with an average 32% reduction in main memory energy.