2020 年 17 巻 14 号 p. 20200198
In this letter, we propose a method to precisely extract on-chip capacitance in a transistor level with the minimal signoff data. As electromagnetic compatibility (EMC) concern in this work, a precise estimation of on-chip capacitance is important for designing a power delivery network (PDN) of LSI-package-board systems. However, the conventional methods require additional libraries other than the signoff data to extract the capacitance in a chip level. The proposed method improves accuracy of the extracted capacitance by simulating the device intrinsic capacitance simultaneously in the transistor level and enabling us to utilize commonly used design resources and flow as well. The experimental results show that the capacitance of a fabricated chip in 130 nm technology estimated by the proposed method is within 8% error compared to the measurement of the capacitance. The whole extraction process can be done within a short period of time.