Optimization of spacer and source/channel junction to improve TFET characteristics

Abstract

As the electrical characteristics of tunnel field-effect transistors (TFETs) are greatly influenced by the source junction and the gate spacer, the effects of these parameters are analyzed by technology computer-aided design simulation. As a result, it is found that an ON-state current of TFETs can be improved by +161.8% through the high-κ spacer of an appropriate length when the source junction does not overlap the edge of the spacer. In addition, it is confirmed that an intrinsic delay time which determines the high frequency characteristics is also reduced by -65.9% because an increase of entire gate capacitance, a side effect of the high-κ spacer, is negligible.