A modified pulse swallow frequency divider for fractional-N PLL

Abstract

A modified pulse swallow frequency divider for fractional-N frequency synthesizers was designed and implemented in a 0.18 µm CMOS process. The proposed structure inserts a pulser between D flip-flop 1 (DFF1) and B counter to solve the possible malfunction of the SR latch and the unwanted division ratio offset in the conventional structure. To remarkably improve the operating speed, a D flip-flop 2 (DFF2) was employed to retime the modulus control (MC) signal. The proposed frequency divider can work at an input clock signal frequency up to 7.04 GHz with a power consumption of only 7.59 mW.