Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Abstract

The current aggregation mechanism created by the gate structure is proposed for electrostatic discharging (ESD). Through device simulation, the size-expanded gate structure in gate-control dual-direction silicon controlled rectifier (GC-DDSCR) is found to aggregate the surface parasitic current path and the main SCR current path. The SCR current path is consequently twisted and extended to increase the holding voltage (V_h). Two GC-DDSCRs are fabricated in a 0.5µm CMOS technology and tested by transmission line pulse (TLP). The V_h increases from 13.84V to 16.44V as the gate size expands from 2.5µm to 4.5µm. The mechanism of current aggregation is verified.