A memristor-based low-cost multiple-time adaptive offset voltage trimming system for operational amplifier

抄録

Low-offset operational amplifiers are widely employed in readout circuits. Conventional calibration techniques such as chopper or fuse trimming face the inherent contradiction between repetitive calibration and small area and power consumption. Memristors offer a promising alternative with their unique characteristics of continuously variable resistance, repeatable programmability, and compact size. This paper proposes a memristor-based multiple-time adaptive trimming circuit for amplifier offset. A folded cascode two-stage operational amplifier was fabricated using the 180 nm CMOS process and trimmed by the proposed technique. Chip testing demonstrates that it reduces amplifier offset voltage to below 57.8 μV level while occupying only 1829 μm² of circuit area, providing a new low-cost feasible approach for repeatable offset compensation.