A 100 Gb/s PAM4 receiver analog front-end with 33.1-dB boost in 28-nm CMOS process

抄録

This article presents a 100 Gb/s four-level pulse amplitude modulation (PAM4) analog front-end (AFE) implemented in TSMC’s 28-nm CMOS process. The continuous-time linear equalizer (CTLE) employs the transconductance (GM) stage for mid-frequency (MF) peaking, while leveraging the transimpedance (TIA) stage to produce high-frequency (HF) peaking. This allows the HF peak frequency to remain constant as the boost range is adjusted. While the variable gain amplifier (VGA) employs shunt inductive peaking and feedforward technique to extend bandwidth. Both CTLE and VGA use complementary structures to improve linearity. Frequency response tests show the AFE has a 31 GHz peak frequency and a 33.1 dB gain boost. Eye diagram measurements confirm it can open eyes for 100 Gb/s PAM4 signals.