A 16-bit 210 MS/s pipelined ADC with distributed differential reference voltage buffer and foreground calibration

抄録

A 16-bit 210 MSPS pipelined analog-to-digital converter (ADC) with distributed differential reference voltage buffer (DDRVB) and foreground calibration is presented. Current summing and floating current control techniques are used in DDRVB to achieve high precision adjustable reference voltage. In order to improve the power supply rejection ratio (PSRR) and reduce the output impedance and power consumption, the push pull output and replica circuit structure is introduced. A mix-signal foreground calibration method for pipelined ADC is proposed. Offset, gain and mismatch errors in pipelined sub-stage circuits can be compensated by the proposed calibration method. Based on the proposed DDRVB and calibration method, a prototype 16-bit 210 MS/s pipelined ADC is designed and realized in a 1P6M 0.18 μm CMOS process. Test results show, the 16-bit 210 MSPS ADC core achieves the signal-to-noise ratio (SNR) of 77.3 dB and spurious free dynamic range (SFDR) of 101.7 dB, with 5.1 MHz input at full sampling speed, while consumes the power consumption of 495 mW.