INL impact of parasitic capacitance in auto-zero integrators in incremental sigma-delta ADCs

抄録

Integral nonlinearity (INL) is a key parameter of high-precision incremental sigma-delta analog-to-digital converters (ADCs). Spikes in measured INL plots have been encountered at specific points from reported studies, which however, are often ignored. Here, we report that the parasitic capacitance introduced by the reset switch in the auto-zero integrator in incremental ADC leads to output errors and visible spikes in the INL plot. We demonstrate the impact of this phenomenon through simulations and propose a compensation method by introducing symmetrical parasitic capacitance to counteract its effects. The design and improvement are further experimentally verified based on 0.25-μm CMOS process. An extended counting ADC based on incremental ADC with the parasitic capacitance demonstrates an INL of -4.13/+3.27 LSB, while the ADC with added symmetrical parasitic capacitance exhibits smaller spikes and lower INL of -2.14/+2.52 LSB.