Topology optimization for reducing current imbalance in circuit with multichip devices

Abstract

This study proposes a topology optimization approach to reduce current imbalance in a power module with multi parallel-connected devices. In this study, the conductor layout is derived by a density-based topology optimization that minimizes the coefficient of variation (CV) of the device currents under constraints for grayscale suppression, open/short-circuit prevention, and preservation of the total current. In the optimized results with 12 parallel devices, several disconnections occurred when open/short circuit prevention and the binarization term were not applied. By incorporating both methods, the optimized layout maintained proper connection and reduced current imbalance.