Metro-on-chip: an efficient physical design technique for congestion reduction

Abstract

Routing congestion is one of the main factors in designing in deep submicron technology that may cause unroutability of the design, signal integrity problems and large delays in detoured wires. In this paper, a new methodology is presented which multiplexes regular nets by asynchronous serial transceivers in the physical design flow in order to improve the congestion of the design. Experimental results show that for the attempted benchmarks, the overflow congestion was reduced by up to 40.03% without any degradation in clock frequency and negligible power consumption overhead.