IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
The design of high holding voltage SCR for whole-chip ESD protection
Yong-Seo KooKwang-Yeob LeeKui-Dong KimJong-Ki Kwon
Author information
JOURNALS FREE ACCESS

2008 Volume 5 Issue 17 Pages 624-630

Details
Abstract

In this paper, we have investigated the electrical characteristics of Silicon Controlled Rectifier (SCR)-based ESD power clamp circuit with high holding voltage for whole-chip ESD protection. The proposed ESD power clamp circuit (HHVSCR: High Holding Voltage SCR) has different well (n/p-well) length (3/7µm - 8/2µm) and p-drift (p+) length (8µm - 16µm). The measurement results indicate that dimension of n/p-well and p-drift has a great effect on holding voltage (2V-5V) and a little effect on the triggering voltage (6.5V∼7V). And the whole-chip ESD protection was designed for 2.5∼3.3V applications, this whole-chip ESD protection design can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. The robustness of the novel ESD protection cells were measured to 6kV (HBM: Human Body Model), 280V (MM: Machine Model).

Information related to the author
© 2008 by The Institute of Electronics, Information and Communication Engineers
Next article
feedback
Top