2008 Volume 5 Issue 2 Pages 67-73
A novel switched-RC sampling MDAC is proposed to obtain high linearity under low-voltage and low-power conditions without significant degradation in speed or causing any reliability problem. Moreover, the proposed MDAC has the capability of working as the front-end stage of a pipelined ADC while its front-end S/H stage has been removed to save power consumption. The proposed techniques have been employed to design a 10-bit 100MSample/s ADC with 1Vp-p, diff input signal in a 90nm CMOS process and 0.9V supply voltage. Results show an SNDR of 59dB and an SFDR of 66dB while consuming 15.8mW power.