IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Implementation of high-speed SHA-1 architecture
Eun-Hee LeeJe-Hoon LeeIl-Hwan ParkKyoung-Rok Cho
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2009 Volume 6 Issue 16 Pages 1174-1179

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Abstract

This paper proposes a new SHA-1 architecture to exploit higher parallelism and to shorten the critical path for Hash operations. It enhances a performance without significant area penalty. We implemented the proposed SHA-1 architecture on FPGA that showed the maximum clock frequency of 118MHz allows a data throughput rate of 5.9Gbps. The throughput is about 26% higher, compared to other counterparts. It supports cryptography of high-speed multimedia data.

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© 2009 by The Institute of Electronics, Information and Communication Engineers
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