A hierarchical and parallel SoC architecture for vision procesor

Abstract

This paper presents a hierarchical and parallel SoC (System on Chip) architecture for vision processor. The vision computing is divided into 3 task level parallel computing modules, which are vision decision, feature reorganization (or pattern generation), feature extraction. In the proposed architecture, there are two separately buses to integrate the 3 computing modules, and also the new interrupt for RISC processor to implement the synchronization between the hardware modules and software. The human-face detecting and tracking application demo has been mapped on the proposed architecture and verified on the FPGA. Architecture performance is also analyzed to show the proposed is more suitable for vision applications with higher image resolution.