IEICE Electronics Express
An energy efficient full adder cell for low voltage
Keivan NaviMehrdad MaeenOmid Hashemipour
Author information

Volume 6 (2009) Issue 9 Pages 553-559

Download PDF (329K) Contact us

This paper presents an area efficient, high-speed and ultra low power 1-bit full adder that uses only 9 transistors. It works based on majority function and MOS capacitors. Because of the simple structure of the proposed design and reduced transistor counts, a very low power full adder is realized. It also can work more reliably at ultra low supply voltage in comparison with the previous designs. The circuit being studied is optimized for energy efficiency at 0.18-µm CMOS process technology. The adder cell is compared to four standard adders based on power consumption, speed and power delay product. Intensive simulation runs on HSPICE shows that the new adder has more than 44% in power savings over conventional CMOS adder and is 10% faster.

Information related to the author
© 2009 by The Institute of Electronics, Information and Communication Engineers
Previous article Next article

Recently visited articles