IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
CMOS latch bit-cell array for low-power SRAM design
Yeonbae ChungWeijie Cheng
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JOURNALS FREE ACCESS

2010 Volume 7 Issue 15 Pages 1145-1151

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Abstract

The design and physical implementation of a low-power SRAM with 4T CMOS latch bit-cell is presented. The memory cells in this work are composed of two cross-coupled inverters without any access transistors. They are accessed by totally novel read and write methods that result in low operating power dissipation in the nature. A 1.8V SRAM test chip has been fabricated in a 0.18µm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30% reduction in read power and 42% reduction in write power compared to the standard 6T SRAM.

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© 2010 by The Institute of Electronics, Information and Communication Engineers
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