IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Two-stage digital I/Q demodulator employing a reconfigurable 16-phase down-mixing technique
Chanyong JeongYoung-Jae MinSoo-Won Kim
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2010 Volume 7 Issue 3 Pages 177-183

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Abstract

This letter presents a new two-stage digital I/Q demodulator employing a reconfigurable 16-phase quadrature intermediate frequency (IF) sampling technique for multistandard wireless systems such as mobile TV applications. The proposed two-stage digital I/Q demodulator provides the flexibility for the multiphase scheme such as a quadrature phase shift keying (QPSK) and 16-quadrature amplitude modulation (QAM) at the level of down-mixing, which introduces an efficient architecture for the following decimation filter. In this letter, the prototype chip has been implemented in a 0.18µm standard CMOS technology and occupied with the active chip area of 0.02mm2. The power consumption of the fabricated chip is 0.42mW with a 1.8V supply voltage at the sampling frequency of 26 MHz. The experimental results show that the proposed two-stage digital I/Q demodulator is suitable for multistandard wireless systems which require small silicon area and low power dissipation.

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© 2010 by The Institute of Electronics, Information and Communication Engineers
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