IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Fully digital clock frequency doubler
Gunok JungGi-Ho ParkUkrae ChoJae Cheol Son
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2010 Volume 7 Issue 6 Pages 416-420

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Abstract

This paper presents a clock frequency doubler, having the function of automatic adjustable duty cycle without feedback loops. The duty cycle amount can be automatically adjustable using digitized delay block and a counter. This simplifies the design structure and allows the circuit to operate over a wide range of input frequency variation. The simulation results show that this frequency doubler operates at a very wide variable input frequency ranging from 650MHz to 1.25GHz.

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© 2010 by The Institute of Electronics, Information and Communication Engineers
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