2011 Volume 8 Issue 1 Pages 45-49
To reduce the contact resistance at source/drain regions in scaled CMOS, control of PtSi work function by alloying with Hf was investigated. Pt(10-20nm)/Hf(0-10nm)/n-Si(100) stacked layers were annealed at 400°C/60min in a flowing N2 ambient to form silicide layer. In the case of alloying with 3-6nm-thick Hf, it was found that barrier height (ΦBn) for electron was linearly reduced from 0.84eV to 0.56eV with Hf thickness in the initial stacked layer, which corresponds to the work function of 4.89eV and 4.61eV, respectively. Furthermore, the reduction of ΦBn could be precisely controlled by 94meV/nm with Hf thickness.