抄録
In this paper we present a high performance and low power media cache structure using a dynamic fetching mechanism. The proposed cache consists of three parts, i.e., a dual direct mapped cache, a fully associative spatial buffer, and a dynamic fetch unit. When a cache miss occurs, the dynamic fetch controller generates fetch signals for one of three block sizes (e.g., 64-byte, 128-byte, or 192-byte) depending on information that is kept on recent block access patterns. Simulation results show that the proposed cache can achieve better performance than a 2-way or 4-way set associative cache with twice as much space. Also, compared with a victim cache, the average memory access time is improved by about 15% on media applications. It is also shown that power consumption of the proposed cache is around 60% lower than other cache systems.
