IEICE Electronics Express
Online ISSN : 1349-2543
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High-speed interface circuit for differential capacitance transducers
Hoon KimIl-Ho RhoWon-Sup Chung
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2011 Volume 8 Issue 2 Pages 96-102

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Abstract

A high-speed capacitance difference-to-sum ratio measurement circuit is presented for differential capacitance transducers. It consists of a switched-capacitor input stage, two sample-and-hold (S/H) circuits followed by voltage-to-current (V/I) converters, and a current-ratio-controlled relaxation oscillator. This circuit offers a square-wave output whose oscillation period is directly proportional to the capacitance difference-to-sum ratio of the transducers. A prototype circuit built using discrete components exhibits conversion sensitivity (period per unit capacitance difference-to-sum ratio) amounting to 400µs and linearity error as low as 0.037%. The maximum conversion time is about 160µs when the capacitance difference-to-sum ratio is 0.4.

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© 2011 by The Institute of Electronics, Information and Communication Engineers
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