IEICE Electronics Express
Online ISSN : 1349-2543
A common-mode BIST technique for fully-differential sample-and-hold circuits
Jun YuanMasayoshi Tachibana
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2012 Volume 9 Issue 13 Pages 1128-1134

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Abstract

This paper presents a Common-Mode (CM) Built-In Self-Test (BIST) technique for Fully-Differential (FD) Sample-and-Hold (S/H) circuits. Based on the CM test setup, the catastrophic and parametric faults in the MOS switches and hold capacitors can be detected by checking the differential outputs, which should vary around the desired CM output of the FD Operational Amplifier (OpAmp) used in the FD S/H circuits under test. The fault simulation results in circuit-level and the layout design using Rohm 0.18-µm CMOS technology are presented to demonstrate the feasibility of the proposed CM BIST technique for FD S/H circuits.

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© 2012 by The Institute of Electronics, Information and Communication Engineers
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