IEICE Electronics Express
Online ISSN : 1349-2543
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS
Jun HanXingxing ZhangYi LiBaoyu XiongYuejun ZhangZhang ZhangZhiyi YuJun HanXu ChengXiaoyang Zeng
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JOURNALS FREE ACCESS

2012 Volume 9 Issue 16 Pages 1355-1361

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Abstract

This paper details the design of a 64×32bit 4-read 2-write register file in TSMC 65nm LP process. The register file avoids cell banking with pseudo-differential sensing scheme. Moreover, this approach enables a fully shareable and completely symmetry cell layout which shows competitive area results. Non-full-swing technique is proposed to avoid over design and improve energy efficiency. As for the timing control module, clocked pull-down circuit cuts off a possible short-current path at high clock frequency. A prototype is implemented in TSMC 65nm LP technology. The measured results demonstrate operation of 0.77GHz, consuming 7.08mW at 1.2V, and occupying 0.018mm2.

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© 2012 by The Institute of Electronics, Information and Communication Engineers
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