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IEICE Electronics Express
Vol. 9 (2012) No. 17 pp. 1397-1401

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http://doi.org/10.1587/elex.9.1397


An energy-efficient tri-level switching scheme based on half of the reference voltage (Vref) is proposed for the successive approximation register (SAR) analogue-to-digital converter (ADC). With respect to the set-and-down switching scheme, the common-mode voltage variation at the input of the comparator reduces. By using Vref/2, the switching energy and the capacitor area are reduced. The proposed scheme achieves 97.26% less switching energy with one forth of the capacitor area as compared to the conventional architecture.

Copyright © 2012 by The Institute of Electronics, Information and Communication Engineers

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