Energy and area-efficient tri-level switching procedure based on half of the reference voltage for SAR ADC

抄録

An energy-efficient tri-level switching scheme based on half of the reference voltage (V_ref) is proposed for the successive approximation register (SAR) analogue-to-digital converter (ADC). With respect to the set-and-down switching scheme, the common-mode voltage variation at the input of the comparator reduces. By using V_ref/2, the switching energy and the capacitor area are reduced. The proposed scheme achieves 97.26% less switching energy with one forth of the capacitor area as compared to the conventional architecture.