J-STAGE Home  >  Publications - Top  > Bibliographic Information

IEICE Electronics Express
Vol. 9 (2012) No. 20 pp. 1611-1616

Language:

http://doi.org/10.1587/elex.9.1611


This paper describes the architecture of a divide-by-N prescaler and a divide-by-N/N+1 dual-modulus prescaler based on a shift register and a multi-input NOR gate. The divide-by-N prescaler has a circuit style similar to a linear feedback shift register (LFSR), except for the fact that a multi-input NOR gate is used instead of XOR gates. This architecture can be applied to various division ratios of N ≥ 2 by changing the numbers of flip-flops and NOR-gate inputs according to specific rules, which will be explained in this paper. The state of the prescaler runs through the correct loop without requiring a reset signal or an initialization circuit.

Copyright © 2012 by The Institute of Electronics, Information and Communication Engineers

Article Tools

Share this Article