Volume 9 (2012) Issue 9 Pages 840-848
In this letter, a high speed compact structure for 2-bit/step successive approximation (SAR) ADC is presented. Using modified algorithm yields to a simple radix-4 DAC with half bit and a resolution independent Reference Generator unit in the proposed design. This in term caused to extend the resolution of SAR ADC structure for double bit resolutions. An 8-bit SAR ADC is implemented and simulated based on the proposed structure in 300MHz clock frequency and 50MS/s sampling rate. The target design has SNDR=43dB and SFDR=52dB for fin=4MHz at 50Ms/s. The achieved power consumption at this sampling rate is 1.04mW and the Figure of Merits of proposed design will be 175fJ/Conversion-step.