IEICE Electronics Express
Synchronous delay based UWB pulse generator in FPGA
Punithavathi DuraiswamyXiao LiJohan BauwelinckJan VandewegePeter VaesStephanie Teughels
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Volume 9 (2012) Issue 9 Pages 868-873

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Abstract

This paper presents an architecture for generating UWB pulses with a high centre frequency accuracy. The architecture allows to generate frequencies twice that of the FPGA clock using synchronous delays and is implementable in all types of FPGA. With a FPGA clock of 150MHz, we generate RF pulse of 300MHz with a maximum fractional bandwidth of 30%. The architecture also allows pulse width increment in steps of the clock period.

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© 2012 by The Institute of Electronics, Information and Communication Engineers
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