A 0.2 V-1.8 V 8T SRAM with Bit-interleaving Capability

Abstract

An 8T SRAM with bit-interleaving capability is designed for ultra-dynamic voltage scaling applications. An adaptive body-biasing scheme is designed to improve the stability of 8T cell, which achieves 1.5 times higher noise margin compared to the non-body-biased 8T cell. Also, a write driver is presented to enable the bit-interleaving structure, thus achieving high soft-error tolerance. A prototype 1-kb SRAM is fabricated in a standard 0.18 µm CMOS process. The measurement results show that the proposed design fulfils the functionality under supply voltage from 1.8V to 0.3V (0.2V when the write wordline is boosted to 0.36V) and the total power is reduced by four times of magnitude.